Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test

There are several significant advantages of memristors, such as their nano scale, fast switching speed, power efficiency and compatibility with CMOS technology, one the alternatives in next generation semiconductor storage devices. D-flip-flops (DFFs) based on traditional process have some shortcomings, including a large area, high power, charge leakage when scaling down. However, memristors offer new approach to design DFFs improved performance. Two simplified edge-triggered proposed reduce number devices via Memristor-Rationed Logic (MRL) method, which utilizes characteristic transmitting signals two-stage inversion structure. In addition, two 4-bit Linear Feedback Shift Registers (LFSRs) designed verified using DFFs. Compared partially existing LFSRs, LFSRs significantly, decrease consumption by 32.7% 33.3% shorten delay time 34.5% 30.7% for NOR NAND gates, respectively. Finally, falling-edge-triggered DFF is used implement major blocks Built-In Self-Test(BIST) circuit, simulation results confirm correctness feasibility.